This invention relates to the field of integrated circuits and more particularly to a method for fabricating and packaging an integrated circuit device.
Historically, integrated circuits (ICs) have comprised a semiconductor die supported by a conductive lead frame. As illustrated in FIG. 1, the typical IC 10 has lead frame leads 12, a die paddle 14, a semiconductor die 16 having a front side with circuitry and a back side, bond wires 18, and encapsulation material or other packaging layer 20. Bond wires 18 attach to bond pads (not depicted) on the front of the die 16. Bond wires provide the connection between the die and the lead frame leads. The leads are attached to printed circuit boards (PCBs) or other devices (not depicted).
The semiconductor industry pursues cost effective and reliable methods to decrease the size of semiconductor packages. The development of the dual in-line package (DIP) has been instrumental in the development of thin small outline packages (TSOPs), tape automated bonding (TAB), and chip-on-board (COB) technologies.
COB assembly processes typically include the steps of bonding a die to a substrate and interconnecting the die to the substrate, using either conventional wire bond or TAB methods.
In reference to FIG. 1, TAB technology has eliminated the lead frame leads 12 and paddle 14, and instead uses TAB tape. TAB tapes comprise a predesigned network of electrical lines and buses which are attached to an IC die. The use of TAB tape and the elimination of lead frames save on fabrication steps and costs. Typically, the die is connected to the TAB tape by a thermocompression or thermosonic bonder.
The prior processes have various disadvantages. Specifically, the testing of IC chips occurs after the TAB tape is attached to a number of die and to the substrate. Thus, when reliability testing takes place, any defective die requires replacement which increases costs. Additionally, by using these processes, several steps occur while the die is unprotected or not encapsulated which can result in additional die defects from increased exposure to the environment.
A semiconductor device and method for forming the device which reduces the problems described above would be desirable.
One skilled in the art will appreciate the advantage of the subject IC and fabrication method for attaching an encapsulated and tested IC die to a PC board. Specifically, a semiconductor packaging technique is disclosed which is cost effective, reliable, and allows for testing of an IC die before it is mounted to TAB tape or soldered to a PC board. Uniquely, several layers of bonded beads are formed and stacked higher than a total IC covering.
Features of the present invention will become apparent from the following detailed description of the illustrated embodiments taken in conjunction with the accompanying drawings.